Infineon TRAVEO T2G - 5.1.33 CPUSS_RAM1_CTL0

Technical Reference Manual 002-29852 Rev. *B
5.1.33 CPUSS_RAM1_CTL0
Description:
RAM 1 control
Address:
0x40201380
Offset:
0x1380
Retention:
Retained
IsDeepSleep:
No
Comment:
This register is for the CPUSS system SRAM controller 1.
Default:
0x30001
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] SLOW_WS [1:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] FAST_WS [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:19] ECC_INJ_E
N [18:18]
ECC_AUTO
_
CORRECT
[17:17]
ECC_EN
[16:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0:1 SLOW_WS RW R 1 See RAM0_CTL.
8:9 FAST_WS RW R 0 See RAM0_CTL.
16 ECC_EN RW R 1 See RAM0_CTL.
17 ECC_AUTO_CORRECT RW R 1 See RAM0_CTL.
18 ECC_INJ_EN RW R 0 See RAM0_CTL.
735
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers