Infineon TRAVEO T2G - 26.8.24 CLK_ILO0_CONFIG

Technical Reference Manual 002-29852 Rev. *B
26.8.24 CLK_ILO0_CONFIG
Description:
ILO0 Configuration
Address:
0x40261508
Offset:
0x1508
Retention:
Retained
IsDeepSleep:
No
Comment:
Configuration register for ILO0. ILO0 configuration and trims are reset by XRES, HIBERNATE,
and power-related resets, unless otherwise noted.
Default:
0x80000000
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] ILO0_BACK
UP [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLE
[31:31]
ILO0_MON
_ENABLE
[30:30]
None [29:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 ILO0_BACKUP RW A 0 This register indicates that ILO0 should stay enabled
during XRES and HIBERNATE modes. If backup
voltage domain is implemented on the product, this bit
also indicates if ILO0 should stay enabled through
power-related resets on other supplies, e.g.. BOD on
VDDD/VCCD. Writes to this field are ignored unless
the WDT is unlocked using WDT_LOCK register. This
register is reset when the backup logic resets.
0: ILO0 turns off during XRES, HIBERNATE, and
power-related resets. ILO0 configuration and trims are
reset by these events.
1: ILO0 stays enabled, as described above. ILO0
configuration and trims are not reset by these events.
30 ILO0_MON_ENABLE RW A 0 Reserved. Always write a zero. Writes to this field are
ignored unless the WDT is unlocked using
WDT_LOCK register.
31 ENABLE RW A 1 Master enable for ILO. Writes to this field are ignored
unless the WDT is unlocked using WDT_LOCK
register.
HT-variant: This register will not clear unless
PWR_CTL2.BGREF_LPMODE==0. After enabling, the
first ILO0 cycle occurs within 12us and is +/-10 percent
accuracy. Thereafter, ILO0 is +/-5 percent accurate.
1663
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers