Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.53 CANFD_CH_TTGTP
Description:
TT Global Time Preset
Address:
0x40520118
Offset:
0x118
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name TP [7:0]
Bits 15 14 13 12 11 10 9 8
Name TP [15:8]
Bits 23 22 21 20 19 18 17 16
Name CTP [23:16]
Bits 31 30 29 28 27 26 25 24
Name CTP [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:15 TP RW R 0 Time Preset
TP is write-protected while TTOST.WGTD is set.
0x0000-7FFF Next Master Reference Mark = Master
Reference Mark + TP
0x8000 reserved
0x8001-FFFF Next Master Reference Mark = Master
Reference Mark - (0x10000 - TP)
16:31 CTP RW R 0 Cycle Time Target Phase
CTP is write-protected while TTOCN.ESCN or
TTOST.SPL are set (see Section 4.11).
0x0000-FFFF Defines target value of cycle time when
a rising edge of m_ttcan_evt is expected
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers