Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
6:7 TMC RW R 0 Register Time Mark Compare
00= No Register Time Mark Interrupt generated
01= Register Time Mark Interrupt if Time Mark = cycle
time
10= Register Time Mark Interrupt if Time Mark = local
time
11= Register Time Mark Interrupt if Time Mark = global
time
8 TTIE RW R 0 Trigger Time Mark Interrupt Pulse Enable
External time mark events are configured by trigger
memory element TMEX (see Section 2.4.7). A
trigger time mark interrupt pulse is generated when the
trigger memory element becomes active,
and the M_TTCAN is in synchronization state
In_Schedule or In_Gap.
0= Trigger Time Mark Interrupt output m_ttcan_tmp
disabled
1= Trigger Time Mark Interrupt output m_ttcan_tmp
enabled
9 GCS RW R 0 Gap Control Select
0= Gap control independent from m_ttcan_evt
1= Gap control by input pin m_ttcan_evt
10 FGP RW R 0 Finish Gap
Set by the CPU, reset by each reference message
0= No reference message requested
1= Application requested start of reference message
11 TMG RW R 0 Time Mark Gap
0= Reset by each reference message
1= Next reference message started when Register
Time Mark interrupt TTIR.RTMI is activated
12 NIG RW R 0 Next is Gap
This bit can only be set when the M_TTCAN is the
actual Time Master and when it is configured for
external event-synchronized time-triggered operation
(TTOCF.GEN = '1')
0= No action, reset by reception of any reference
message
1= Transmit next reference message with
Next_is_Gap = '1'
13 ESCN RW R 0 External Synchronization Control
If enabled the M_TTCAN synchronizes its cycle time
phase to an external event signaled by a rising
edge at pin m_ttcan_evt (see Section 4.11).
0= External synchronization disabled
1= External synchronization enabled
15 LCKC R RW 0 TT Operation Control Register Locked
Set by a write access to register TTOCN. Reset when
the updated configuration has been
synchronized into the CAN clock domain.
0= Write access to TTOCN enabled
1= Write access to TTOCN locked
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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