Infineon TRAVEO T2G - 13.5.1.11 FAULT_STRUCT_INTR_SET

Technical Reference Manual 002-29852 Rev. *B
13.5.1.11 FAULT_STRUCT_INTR_SET
Description:
Interrupt set
Address:
0x402100C4
Offset:
0xC4
Retention:
Not Retained
IsDeepSleep:
No
Comment:
When read, this register reflects the INTR register. For debug purposes, SW can write a '1' to
activate a specific interrupt cause (this allows for debug of the SW ISR, without relying on HW
to activate the interrupt cause).
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] FAULT [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 FAULT RW1S A 0 SW writes a '1' to this field to set the corresponding
field in the INTR register.
932
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers