Infineon TRAVEO T2G - 5.1.29 CPUSS_CM4_PWR_DELAY_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.29 CPUSS_CM4_PWR_DELAY_CTL
Description:
CM4 power control
Address:
0x40201204
Offset:
0x1204
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x12C
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name UP [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] UP [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:9 UP RW R 300 Number clock cycles delay needed after power domain
power up
731
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