Infineon TRAVEO T2G - 4.13 Register Details; 4.13.1 ITM; 4.13.1.1 CM4_ITM_STIM

Technical Reference Manual 002-29852 Rev. *B
4.13 Register Details
4.13.1 ITM
4.13.1.1 CM4_ITM_STIM
Description:
Stimulus Port registers
Address:
0xE0000000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
The ITM_STIMx register characteristics are:
Purpose: Provide the interface for generating instrumentation messages.
Usage constraints:
- Accessible by word-aligned byte, halfword, and word accesses.
- The number of ITM_STIM registers is an IMPLEMENTATION DEFINED multiple of eight,
see Trace Privilege Register, ITM_TPR on page C1-775.
- When DEMCR.TRCENA is 0, the ITM_STIM registers are UNKNOWN on reads and ignore
writes.
Configurations: Always implemented.
Attributes: See Arm TRM Table C1-11 on page C1-773, and the register field descriptions.
The address of ITM_STIMn is (0xE0000000 + 4n).
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name STIMULUS [7:0]
Bits 15 14 13 12 11 10 9 8
Name STIMULUS [15:8]
Bits 23 22 21 20 19 18 17 16
Name STIMULUS [23:16]
Bits 31 30 29 28 27 26 25 24
Name STIMULUS [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 STIMULUS RW R X Data write to the stimulus port FIFO, for forwarding as
a software event packet.
When read, bit[0] indicates whether the stimulus port
FIFO can accept data:
0: Stimulus port FIFO full.
1: Stimulus port FIFO can accept at least one word.
This bit is UNKNOWN after a Power-on reset.
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2022-04-18
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