Infineon TRAVEO T2G - 26.8.50.7 MCWDT_INTR

Technical Reference Manual 002-29852 Rev. *B
26.8.50.7 MCWDT_INTR
Description:
MCWDT Interrupt Register
Address:
0x402680A0
Offset:
0xA0
Retention:
Retained
IsDeepSleep:
No
Comment:
Interrupt status register for MCWDT subcounters.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] CTR2_INT
[2:2]
CTR1_INT
[1:1]
CTR0_INT
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 CTR0_INT RW1C A 0 MCWDT Interrupt Request for sub-counter 0. This bit
is set by hardware as configured by this registers. This
bit must be cleared by firmware.
1 CTR1_INT RW1C A 0 MCWDT Interrupt Request for sub-counter 1. This bit
is set by hardware as configured by this registers. This
bit must be cleared by firmware.
2 CTR2_INT RW1C A 0 MCWDT Interrupt Request for sub-counter 2. This bit
is set by hardware as configured by this registers. This
bit must be cleared by firmware.
1711
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers