Infineon TRAVEO T2G - 4.13.11.14 CM4_TPIU_CLAIMSET

Technical Reference Manual 002-29852 Rev. *B
4.13.11.14 CM4_TPIU_CLAIMSET
Description:
Claim Tag Set Register
Address:
0xE008EFA0
Offset:
0xFA0
Retention:
Retained
IsDeepSleep:
No
Comment:
This register forms one half of the Claim Tag value. This location allows individual bits to be
set, write, and returns the number of bits that can be set, read.
You can determine how many claim bits are implemented by reading this register. For
example, if 4 bits are implemented, a read of this register will return 0x0000000F. If no claim
tag is implemented, then a read of this register will return 0x00000000.
Default:
0xF
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:4] TAG [3:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:3 TAG RW1S R 15 A bit programmable register bank which sets the Claim
Tag Value. A read will return a logic 1 for all
implemented locations.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers