Infineon TRAVEO T2G - 7.5.3.14 CXPI_CH_RX_FIFO_STATUS

Technical Reference Manual 002-29852 Rev. *B
7.5.3.14 CXPI_CH_RX_FIFO_STATUS
Description:
RX FIFO status
Address:
0x405180A4
Offset:
0xA4
Retention:
Not Retained
IsDeepSleep:
No
Comment:
This register contains RX FIFO control
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] USED [4:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:21] AVAIL [20:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:4 USED R W 0 Number of used/occupied entries in the RX FIFO. The
field value is in the range [0, 16]. When '0', the RX
FIFO is empty. When '16', the RX FIFO is full.
16:20 AVAIL R W Undefined RX FIFO avail
0-No content in RX FIFO
1-1 available content in RX FIFO.
2-2 available content in RX FIFO.
..
16-16 available content in RX FIFO.
Note that the Fifo Width is 1Byte and each content in
this context means 1 fifo slot. The number of bytes in
each slot are determine through the number of data
bytes in a message frame.
(RXPID_FI.FI/RXPID_FI.DLCEXT)
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers