Infineon TRAVEO T2G - 2.3.9.6.34 CANFD_CH_TXBC

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.34 CANFD_CH_TXBC
Description:
Tx Buffer Configuration
Address:
0x405200C0
Offset:
0xC0
Retention:
Retained
IsDeepSleep:
No
Comment:
Protected Write.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [1:0]
Bits 15 14 13 12 11 10 9 8
Name TBSA [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:22] NDTB [21:16]
Bits 31 30 29 28 27 26 25 24
Name None
[31:31]
TFQM
[30:30]
TFQS [29:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
2:15 TBSA RW R 0 Tx Buffers Start Address
Start address of Tx Buffers section in Message RAM
(32-bit word address, see Figure 2).
16:21 NDTB RW R 0 Number of Dedicated Transmit Buffers
0= No Dedicated Tx Buffers
1-32= Number of Dedicated Tx Buffers
32= Values greater than 32 are interpreted as 32
24:29 TFQS RW R 0 Transmit FIFO/Queue Size
0= No Tx FIFO/Queue
1-32= Number of Tx Buffers used for Tx FIFO/Queue
32= Values greater than 32 are interpreted as 32
30 TFQM RW R 0 Tx FIFO/Queue Mode
0= Tx FIFO operation
1= Tx Queue operation
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers