Infineon TRAVEO T2G - 3.8.3.14 CM0 P_SCS_SCR

Technical Reference Manual 002-29852 Rev. *B
3.8.3.14 CM0P_SCS_SCR
Description:
System Control Register
Address:
0xE000ED10
Offset:
0xD10
Retention:
Retained
IsDeepSleep:
No
Comment:
Sets or returns system control data.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] SEVONPEND
[4:4]
None [3:3] SLEEPDEEP
[2:2]
SLEEPONEX
IT [1:1]
None [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
1 SLEEPONEXIT RW R 0 Determines whether, on an exit from an ISR that
returns to the base level of execution priority, the
processor enters a sleep state:
0 do not enter sleep state.
1 enter sleep state.
See Power management on Arm TRM page B1-240
for more information.
2 SLEEPDEEP RW R 0 An implementation can use this bit to select
DeepSleep power modes upon execution of WFI/WFE:
0: Select Sleep mode
1: Select DeepSleep
4 SEVONPEND RW R 0 Determines whether an interrupt transition from
inactive state to pending state is a wakeup event:
0: transitions from inactive to pending are not wakeup
events.
1: transitions from inactive to pending are wakeup
events.
See WFE on Arm TRM page A6-197 for more
information.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers