Infineon TRAVEO T2G - 5.1.42 CPUSS_BUFF_CTL

Technical Reference Manual 002-29852 Rev. *B
5.1.42 CPUSS_BUFF_CTL
Description:
Buffer control
Address:
0x40201500
Offset:
0x1500
Retention:
Retained
IsDeepSleep:
No
Comment:
The ARM CM0+ and CM4 CPUs use bufferable write transfers to the peripherals by default.
As a result, CPU completion of the write transfer does not guarantee that the write transfer
reached its destination, as the transfer may be buffered/posted in the bus infrastructure.
Moreover, it is possible that the write transfer does not take place at all due to a PPU violation
or a slave error, and in this case the resulting bus error response is not passed to the CPU.
This may cause complications if the CPU assumes that completion of the write transfer implies
that the write transfer has taken effect in a peripheral (e.g. clearing a peripheral's interrupt
cause field). There are multiple possibilities to address this complication:
- Follow the write transfer with a read transfer from the same address, and check that the read
data matches the expectation.
- Configure a fault structure such that the following faults are reported: MS_PPU_0 to
MS_PPU_3 to report PPU violations, timeout or bus errors in the PERI master interfaces, and
GROUP_FAULT_0 to GROUP_FAULT_15 (only for the existing peripheral groups) to report
decoder or peripheral bus errors in the peripheral groups. The CPU can perform a read
transfer after a series of write transfers to the same peripheral group. If the read transfer
completes and no faults are reported, then the write transfers have been executed. Note that
the fault reporting has some latency, so the faults may be reported after the completion of the
read transfer.
- Use the CPU MPU to set write transfers to non-bufferable/non-posted.
- Use BUFF_CTL.WRITE_BUFF to ensure that all write transfers are non-bufferable/non-
posted
Note: the CM4 CPU has an internal ACTLR.DISDEFWBUF register field that controls write
transfers (the CM0_ CPU does NOT have this register).
Default:
0x1
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] WRITE
_BUFF [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 WRITE_BUFF RW R 1 Specifies if write transfer can be buffered in the bus
infrastructure bridges:
'0': Write transfers are not buffered, independent of the
transfer's bufferable attribute.
'1': Write transfers can be buffered, if the transfer's
bufferable attribute indicates that the transfer is a
bufferable/posted write.
745
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers