Technical Reference Manual 002-29852 Rev. *B
9.3.18.8 DW_CH_STRUCT_INTR_MASKED
Description:
Interrupt masked
Address:
0x4028801C
Offset:
0x1C
Retention:
Not Retained
IsDeepSleep:
No
Comment:
When read, this register reflects a bitwise AND between the INTR and INTR_MASK registers.
This register allows SW to read the status of all mask enabled interrupt causes with a single
load operation, rather than two load operations: one for INTR and one for INTR_MASK. This
simplifies Firmware development. The associated interrupt is active ('1'), when
INTR_MASKED != 0.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] CH [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 CH R W 0 Logical and of corresponding INTR and INTR_MASK
fields.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
To Next Page
Loading...
