Infineon TRAVEO T2G - 26.8.37 CLK_PLL_STATUS

Technical Reference Manual 002-29852 Rev. *B
26.8.37 CLK_PLL_STATUS
Description:
PLL Status Register
Address:
0x40261640
Offset:
0x1640
Retention:
Retained
IsDeepSleep:
No
Comment:
This register indicates status for the PLL. There is a copy of this register for each PLL. This
register is synchronized during an AHB read transaction. This causes a number wait-states to
be inserted in the transaction depending on the frequency ration between system and PLL
frequency.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] UNLOCK
_OC
CURRED
[1:1]
LOCKED
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 LOCKED R W 0 PLL Lock Indicator
1 UNLOCK_OCCURRED RW1C A 0 This bit sets whenever the PLL Lock bit goes low, and
stays set until cleared by firmware.
1681
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers