Infineon TRAVEO T2G - 7.5.3.20 CXPI_CH_INTR_MASKED

Technical Reference Manual 002-29852 Rev. *B
7.5.3.20 CXPI_CH_INTR_MASKED
Description:
Interrupt masked
Address:
0x405180CC
Offset:
0xCC
Retention:
Not Retained
IsDeepSleep:
No
Comment:
When read, this register reflects a bitwise AND between the INTR and INTR_MASK registers.
This register allows SW to read the status of all mask enabled interrupt causes with a single
load operation, rather than two load operations: one for INTR and one for INTR_MASK. This
simplifies Firmware development. The associated interrupt is active ('1'), when
INTR_MASKED != 0.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] TX_FIFO_T
RIGGER
[4:4]
TX
_WAKEUP
_DONE
[3:3]
None [2:2] TX
_RESPON
SE_DONE
[1:1]
TX
_HEADER
_DONE
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:14] TXRX
_COMP
LETE
[13:13]
RX
_HEADER
_PID
_DONE
[12:12]
RX_FIFO_T
RIGGER
[11:11]
RX
_WAKEUP
_DETECT
[10:10]
RX
_RESPON
SE_DONE
[9:9]
RX
_HEADER
_DONE
[8:8]
Bits 23 22 21 20 19 18 17 16
Name RX_DATA
_LENGTH
_ERROR
[23:23]
RX
_HEADER
_PARITY
_ERROR
[22:22]
RX_CRC
_ERROR
[21:21]
TX_BIT_ER
ROR
[20:20]
TX
_HEADER
_ARB
_LOST
[19:19]
TIMEOUT
[18:18]
None [17:16]
Bits 31 30 29 28 27 26 25 24
Name None
[31:31]
TX_FRAME
_ERROR
[30:30]
RX_FRAME
_ERROR
[29:29]
TX
_UNDERF
LOW
_ERROR
[28:28]
RX
_UNDERF
LOW
_ERROR
[27:27]
TX
_OVERFL
OW
_ERROR
[26:26]
RX
_OVERFL
OW
_ERROR
[25:25]
TX_DATA
_LENGTH
_ERROR
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 TX_HEADER_DONE R W 0 Logical AND of corresponding INTR and INTR_MASK
fields.
1 TX_RESPONSE_DONE R W 0 Logical AND of corresponding INTR and INTR_MASK
fields.
3 TX_WAKEUP_DONE R W 0 Logical AND of corresponding INTR and INTR_MASK
fields.
4 TX_FIFO_TRIGGER R W 0 Logical AND of corresponding INTR and INTR_MASK
fields.
8 RX_HEADER_DONE R W 0 Logical AND of corresponding INTR and INTR_MASK
fields.
9 RX_RESPONSE_DONE R W 0 Logical AND of corresponding INTR and INTR_MASK
fields.
10 RX_WAKEUP_DETECT R W 0 Logical AND of corresponding INTR and INTR_MASK
fields.
11 RX_FIFO_TRIGGER R W 0 Logical AND of corresponding INTR and INTR_MASK
fields.
798
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers