Infineon TRAVEO T2G - 4.13.5.36 CM4_ETM_PID3

Technical Reference Manual 002-29852 Rev. *B
4.13.5.36 CM4_ETM_PID3
Description:
Peripheral Identification Register 3.
Address:
0xE0041FEC
Offset:
0xFEC
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name ECOREVNUM [7:4] None [3:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
4:7 ECOREVNUM R R 0 Refer ARM documentation. See links in CM4_ETM.CR
register.
478
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers