Infineon TRAVEO T2G - 19.5.1.18 CH; 19.5.1.18.1 PASS_SAR_CH_TR_CTL

Technical Reference Manual 002-29852 Rev. *B
19.5.1.18 CH
19.5.1.18.1 PASS_SAR_CH_TR_CTL
Description:
Trigger control.
Address:
0x40900800
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
Make sure the channel or the IP is disabled before changing this register
Default:
0x800
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:7] PRIO [6:4] None [3:3] SEL [2:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:12] GROUP
_END
[11:11]
None
[10:10]
PREEMPT_TYPE [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name DONE
_LEVEL
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:2 SEL RW R 0 Trigger select
OFF 0 Use for channels in group, except the first channel
TCPWM 1 Trigger from corresponding TCPWM channel
GENERIC0 2 Generic trigger input 0
GENERIC1 3 N/A
GENERIC2 4 N/A
GENERIC3 5 N/A
GENERIC4 6 N/A
CONTINUOUS 7 Always triggered (also called idle), can only be used
for at most 1 channel
4:6 PRIO RW R 0 Channel priority:
'0': highest priority.
'1'
...
'6'
'7': lowest priority.
Channels with the same priority constitute a priority
level. Priority decoding determines the highest priority
pending channel. This channel is determined as
follows. First, the highest priority level with pending
channels is identified. Second, within this priority level,
round robin arbitration is applied. Round robin
arbitration (within a priority level) gives the highest
priority to the lower channel indices (within the priority
level).
8:9 PREEMPT_TYPE RW R 0 Preemption type allow for this group
1107
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers