Infineon TRAVEO T2G - 28.2.3 CNT 2; 28.2.4 CNT 3; 28.2.5 CNT 4

Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
TCPWM0_GRP1_CNT1_TR_PWM_CTRL
0x403880D0 FULL Counter trigger PWM control register
TCPWM0_GRP1_CNT1_TR_OUT_SEL
0x403880D4 FULL Counter output trigger selection register
TCPWM0_GRP1_CNT1_INTR
0x403880F0 FULL Interrupt request register
TCPWM0_GRP1_CNT1_INTR_SET
0x403880F4 FULL Interrupt set request register
TCPWM0_GRP1_CNT1_INTR_MASK
0x403880F8 FULL Interrupt mask register
TCPWM0_GRP1_CNT1_INTR_MASKED
0x403880FC FULL Interrupt masked request register
28.2.3 CNT 2
Register Name Address Permission Description
TCPWM0_GRP1_CNT2_CTRL
0x40388100 FULL Counter control register
TCPWM0_GRP1_CNT2_STATUS
0x40388104 FULL Counter status register
TCPWM0_GRP1_CNT2_COUNTER
0x40388108 FULL Counter count register
TCPWM0_GRP1_CNT2_CC0
0x40388110 FULL Counter compare/capture 0 register
TCPWM0_GRP1_CNT2_CC0_BUFF
0x40388114 FULL Counter buffered compare/capture 0 register
TCPWM0_GRP1_CNT2_CC1
0x40388118 FULL Counter compare/capture 1 register
TCPWM0_GRP1_CNT2_CC1_BUFF
0x4038811C FULL Counter buffered compare/capture 1 register
TCPWM0_GRP1_CNT2_PERIOD
0x40388120 FULL Counter period register
TCPWM0_GRP1_CNT2_PERIOD_BUFF
0x40388124 FULL Counter buffered period register
TCPWM0_GRP1_CNT2_LINE_SEL
0x40388128 FULL Counter line selection register
TCPWM0_GRP1_CNT2_LINE_SEL_BUFF
0x4038812C FULL Counter buffered line selection register
TCPWM0_GRP1_CNT2_DT
0x40388130 FULL Counter PWM dead time register
TCPWM0_GRP1_CNT2_TR_CMD
0x40388140 FULL Counter trigger command register
TCPWM0_GRP1_CNT2_TR_IN_SEL0
0x40388144 FULL Counter input trigger selection register 0
TCPWM0_GRP1_CNT2_TR_IN_SEL1
0x40388148 FULL Counter input trigger selection register 1
TCPWM0_GRP1_CNT2_TR_IN_EDGE_SEL
0x4038814C FULL Counter input trigger edge selection register
TCPWM0_GRP1_CNT2_TR_PWM_CTRL
0x40388150 FULL Counter trigger PWM control register
TCPWM0_GRP1_CNT2_TR_OUT_SEL
0x40388154 FULL Counter output trigger selection register
TCPWM0_GRP1_CNT2_INTR
0x40388170 FULL Interrupt request register
TCPWM0_GRP1_CNT2_INTR_SET
0x40388174 FULL Interrupt set request register
TCPWM0_GRP1_CNT2_INTR_MASK
0x40388178 FULL Interrupt mask register
TCPWM0_GRP1_CNT2_INTR_MASKED
0x4038817C FULL Interrupt masked request register
28.2.4 CNT 3
Register Name Address Permission Description
TCPWM0_GRP1_CNT3_CTRL
0x40388180 FULL Counter control register
TCPWM0_GRP1_CNT3_STATUS
0x40388184 FULL Counter status register
TCPWM0_GRP1_CNT3_COUNTER
0x40388188 FULL Counter count register
TCPWM0_GRP1_CNT3_CC0
0x40388190 FULL Counter compare/capture 0 register
TCPWM0_GRP1_CNT3_CC0_BUFF
0x40388194 FULL Counter buffered compare/capture 0 register
TCPWM0_GRP1_CNT3_CC1
0x40388198 FULL Counter compare/capture 1 register
TCPWM0_GRP1_CNT3_CC1_BUFF
0x4038819C FULL Counter buffered compare/capture 1 register
TCPWM0_GRP1_CNT3_PERIOD
0x403881A0 FULL Counter period register
TCPWM0_GRP1_CNT3_PERIOD_BUFF
0x403881A4 FULL Counter buffered period register
TCPWM0_GRP1_CNT3_LINE_SEL
0x403881A8 FULL Counter line selection register
TCPWM0_GRP1_CNT3_LINE_SEL_BUFF
0x403881AC FULL Counter buffered line selection register
TCPWM0_GRP1_CNT3_DT
0x403881B0 FULL Counter PWM dead time register
TCPWM0_GRP1_CNT3_TR_CMD
0x403881C0 FULL Counter trigger command register
TCPWM0_GRP1_CNT3_TR_IN_SEL0
0x403881C4 FULL Counter input trigger selection register 0
TCPWM0_GRP1_CNT3_TR_IN_SEL1
0x403881C8 FULL Counter input trigger selection register 1
TCPWM0_GRP1_CNT3_TR_IN_EDGE_SEL
0x403881CC FULL Counter input trigger edge selection register
TCPWM0_GRP1_CNT3_TR_PWM_CTRL
0x403881D0 FULL Counter trigger PWM control register
TCPWM0_GRP1_CNT3_TR_OUT_SEL
0x403881D4 FULL Counter output trigger selection register
TCPWM0_GRP1_CNT3_INTR
0x403881F0 FULL Interrupt request register
TCPWM0_GRP1_CNT3_INTR_SET
0x403881F4 FULL Interrupt set request register
TCPWM0_GRP1_CNT3_INTR_MASK
0x403881F8 FULL Interrupt mask register
TCPWM0_GRP1_CNT3_INTR_MASKED
0x403881FC FULL Interrupt masked request register
28.2.5 CNT 4
Register Name Address Permission Description
TCPWM0_GRP1_CNT4_CTRL
0x40388200 FULL Counter control register
TCPWM0_GRP1_CNT4_STATUS
0x40388204 FULL Counter status register
TCPWM0_GRP1_CNT4_COUNTER
0x40388208 FULL Counter count register
TCPWM0_GRP1_CNT4_CC0
0x40388210 FULL Counter compare/capture 0 register
1781
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers