Infineon TRAVEO T2G - 13.5 Register Details; 13.5.1 STRUCT; 13.5.1.1 FAULT_STRUCT_CTL

Technical Reference Manual 002-29852 Rev. *B
13.5 Register Details
13.5.1 STRUCT
13.5.1.1 FAULT_STRUCT_CTL
Description:
Fault control
Address:
0x40210000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
This register uses DeepSleep reset. Therefore, a DeepSleep reset (possibly as a result of
CTL.RESET_EN) resets this register (including setting CTL.RESET_EN to '0').
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] RESET
_REQ_EN
[2:2]
OUT_EN
[1:1]
TR_EN
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 TR_EN RW R 0 Trigger output enable:
'0': Disabled. The trigger output 'tr_fault' is '0'.
'1': Enabled. The trigger output 'tr_fault' reflects
STATUS.VALID. The trigger can be used to initiate a
Datawire transfer of the FAULT data (FAULT_DATA0
through FAULT_DATA3).
1 OUT_EN RW R 0 IO output signal enable:
'0': Disabled. The IO output signal 'fault_out' is '0'. The
IO output enable signal 'fault_out_en' is '0'.
'1': Enabled. The IO output signal 'fault_out' reflects
STATUS.VALID. The IO output enable signal
'fault_out_en' is '1'.
2 RESET_REQ_EN RW R 0 Reset request enable:
'0': Disabled.
'1': Enabled. The output reset request signal
'fault_reset_req' reflects STATUS.VALID. This reset
causes a warm/soft/core reset. This warm/soft/core
reset does not affect the fault logic STATUS, DATA0,
..., DATA3 registers (allowing for post soft reset failure
analysis).
The 'fault_reset_req' signals of the individual fault
report structures are combined (logically OR'd) into a
single SRSS 'fault_reset_req' signal.
917
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers