Infineon TRAVEO T2G - 4.13.10.17 CM4_ETB_ITATBCTR0

Technical Reference Manual 002-29852 Rev. *B
4.13.10.17 CM4_ETB_ITATBCTR0
Description:
Integration Register
Address:
0xE008DEF8
Offset:
0xEF8
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name VALUE [7:0]
Bits 15 14 13 12 11 10 9 8
Name VALUE [15:8]
Bits 23 22 21 20 19 18 17 16
Name VALUE [23:16]
Bits 31 30 29 28 27 26 25 24
Name VALUE [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 VALUE R R 0 Refer CoreSight TRM for details of register description.
See link in TRC_CSTF.CSTFCTL register.
623
2022-04-18
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