Infineon TRAVEO T2G - 20.30.5 PERI_DIV_8_CTL

Technical Reference Manual 002-29852 Rev. *B
20.30.5 PERI_DIV_8_CTL
Description:
Divider control (for 8.0 divider)
Address:
0x40001000
Offset:
0x1000
Retention:
Retained
IsDeepSleep:
No
Comment:
Smallest of the divider types.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] EN [0:0]
Bits 15 14 13 12 11 10 9 8
Name INT8_DIV [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 EN R RW 0 Divider enabled. HW sets this field to '1' as a result of
an ENABLE command. HW sets this field to '0' as a
result on a DISABLE command.
Note that this field is retained. As a result, the divider
does NOT have to be re-enabled after transitioning
from DeepSleep to Active power mode.
8:15 INT8_DIV RW R 0 Integer division by (1+INT8_DIV). Allows for integer
divisions in the range [1, 256]. Note: this type of divider
does NOT allow for a fractional division.
For the generation of a divided clock, the integer
division range is restricted to [2, 256].
For the generation of a 50/50 percent duty cycle digital
divided clock, the integer division range is restricted to
even numbers in the range [2, 256]. The generation of
a 50/50 percent duty cycle analog divided clock has no
restrictions.
Note that this field is retained. However, the counter
that is used to implement the division is not and will be
initialized by HW to '0' when transitioning from
DeepSleep to Active power mode.
1146
2022-04-18
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