Infineon TRAVEO T2G - 26.8.11 SRSS_INTR_MASKED

Technical Reference Manual 002-29852 Rev. *B
26.8.11 SRSS_INTR_MASKED
Description:
SRSS Interrupt Masked Register
Address:
0x4026020C
Offset:
0x20C
Retention:
Retained
IsDeepSleep:
Yes
Comment:
Bitwise and between the interrupt request and mask registers so firmware can read the status
of all mask enabled interrupt causes with a single load operation
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:6] CLK_CAL
[5:5]
None [4:3] HVLVD2
[2:2]
HVLVD1
[1:1]
None [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
1 HVLVD1 R RW 0 Logical and of corresponding request and mask bits.
2 HVLVD2 R RW 0 Logical and of corresponding request and mask bits.
5 CLK_CAL R RW 0 Logical and of corresponding request and mask bits.
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2022-04-18
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