Infineon TRAVEO T2G - 8.5.3.4 DMAC_CH_DST

Technical Reference Manual 002-29852 Rev. *B
8.5.3.4 DMAC_CH_DST
Description:
Channel current destination address
Address:
0x402A1018
Offset:
0x18
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name ADDR [7:0]
Bits 15 14 13 12 11 10 9 8
Name ADDR [15:8]
Bits 23 22 21 20 19 18 17 16
Name ADDR [23:16]
Bits 31 30 29 28 27 26 25 24
Name ADDR [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 ADDR R W Undefined Current address of destination location.
808
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers