Technical Reference Manual 002-29852 Rev. *B
26.8.6 CLK_CAL_CNT1
Description:
Clock Calibration Counter 1
Address:
0x40260148
Offset:
0x148
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x80000000
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name CAL_COUNTER1 [7:0]
Bits 15 14 13 12 11 10 9 8
Name CAL_COUNTER1 [15:8]
Bits 23 22 21 20 19 18 17 16
Name CAL_COUNTER1 [23:16]
Bits 31 30 29 28 27 26 25 24
Name CAL
_COUNT
ER_DONE
[31:31]
None [30:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0:23 CAL_COUNTER1 RW A 0 Down-counter clocked on fast clock output #0 (see
CLK_OUTPUT_FAST). This register always reads as
zero. Counting starts internally when this register is
written with a nonzero value. CAL_COUNTER_DONE
goes immediately low to indicate that the counter has
started and will be asserted when the counters are
done. Do not write this field unless
CAL_COUNTER_DONE==1. Both clocks must be
running or the measurement will not complete. A
stalled counter can be recovered by selecting valid
clocks, waiting until the measurement completes, and
discarding the first result.
31 CAL_COUNTER_DONE R W 1 Status bit indicating that the internal counter #1 is
finished counting and CLK_CAL_CNT2.COUNTER
stopped counting up
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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