Infineon TRAVEO T2G - 9.3.12 DW_CRC_CTL

Technical Reference Manual 002-29852 Rev. *B
9.3.12 DW_CRC_CTL
Description:
CRC control
Address:
0x40280100
Offset:
0x100
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] DATA
_REVERSE
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:9] REM
_REVERSE
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 DATA_REVERSE RW R 0 Specifies the bit order in which a data Byte is
processed (reversal is performed after XORing):
'0': Most significant bit (bit 1) first.
'1': Least significant bit (bit 0) first.
8 REM_REVERSE RW R 0 Specifies whether the remainder is bit reversed
(reversal is performed after XORing):
'0': No.
'1': Yes.
873
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers