Infineon TRAVEO T2G - 8.5 Register Details; 8.5.1 DMAC_CTL

Technical Reference Manual 002-29852 Rev. *B
8.5 Register Details
8.5.1 DMAC_CTL
Description:
Control
Address:
0x402A0000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLED
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
31 ENABLED RW R 0 IP enable:
'0': Disabled. All non-retention registers (command and
status registers) are reset to their default value when
the IP is disabled. All retention registers retain their
value when the IP is disabled.
'1': Enabled.
DISABLED 0 N/A
ENABLED 1 N/A
802
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers