Infineon TRAVEO T2G - 18.13.3 CH; 18.13.3.1 LIN_CH_CTL0

Technical Reference Manual 002-29852 Rev. *B
18.13.3 CH
18.13.3.1 LIN_CH_CTL0
Description:
Control 0
Address:
0x40508000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x400C0101
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] AUTO_EN
[4:4]
None [3:2] STOP_BITS [1:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] BREAK_DELIMITER_LEN
GTH [9:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:21] BREAK_WAKEUP_LENGTH [20:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLED
[31:31]
FILTER_EN
[30:30]
PARITY
_EN [29:29]
PARITY
[28:28]
BIT
_ERROR
_IGNORE
[27:27]
None [26:25] MODE
[24:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:1 STOP_BITS RW R 1 STOP bit periods:
'0': 1/2 bit period.
'1': 1 bit period.
'2': 1 1/2 bit period.
'3': 2 bit periods.
In LIN mode, this field should be set to '1' (the default
value) .
In UART mode, this field can be programmed as
desired.
Note: receiver STOP bit frame errors can only be
detected if the number of STOP bit periods is 1 or
more bit period.
4 AUTO_EN RW R 0 LIN transceiver auto enable:
'0': Disabled.
'1': Enabled. The TX_RX_STATUS.EN_OUT field is
controlled by HW.
1045
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers