Infineon TRAVEO T2G - 23.9.23 SCB_RX_CTRL

Technical Reference Manual 002-29852 Rev. *B
23.9.23 SCB_RX_CTRL
Description:
Receiver control
Address:
0x40600300
Offset:
0x300
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x107
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] DATA_WIDTH [4:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] MEDIAN
[9:9]
MSB
_FIRST
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:4 DATA_WIDTH RW R 7 Dataframe width. DATA_WIDTH + 1 is the expected
amount of bits in received data frame. This number
does not include start, parity and stop bits. For UART
mode, the valid range is [3, 8]. For SPI, the valid range
is [3, 31]. For I2C the only valid value is 7. In EZ mode
(for both SPI and I2C), the only valid value is 7.
8 MSB_FIRST RW R 1 Least significant bit first ('0') or most significant bit first
('1'). For I2C, this field should be '1'.
9 MEDIAN RW R 0 Median filter. When '1', a digital 3 taps median filter is
performed on input interface lines. This filter should
reduce the susceptibility to errors. However, its
requires higher oversampling values. For UART IrDA
submode, this field should always be '1'.
1421
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers