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Infineon TRAVEO T2G - Page 1648

Infineon TRAVEO T2G
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Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
20:23 POLARITY_HIBPIN RW A 0 Each bit sets the active polarity of the corresponding
wakeup pin.
0: Pin input of 0 will wakeup the part from HIBERNATE
1: Pin input of 1 will wakeup the part from HIBERNATE
24:27 MASK_HIBPIN RW A 0 When set, HIBERNATE will wakeup if the
corresponding pin input matches the
POLARITY_HIBPIN setting. Each bit corresponds to
one of the wakeup pins.
30 HIBERNATE_DISABLE RW1S R 0 Hibernate disable bit.
0: Normal operation, HIBERNATE works as described
1: Further writes to this register are ignored
Note: This bit is a write-once bit until the next reset.
Avoid changing any other bits in this register while
disabling HIBERNATE mode. Also, it is recommended
to clear the UNLOCK code, if it was previously written..
31 HIBERNATE RW A 0 Firmware sets this bit to enter HIBERNATE mode. The
system will enter HIBERNATE mode immediately after
writing to this bit and will wakeup only in response to
XRES or WAKEUP event. Both UNLOCK and
FREEZE must have been set correctly in a previous
write operations. Otherwise, it will not enter
HIBERNATE. External supplies must have been stable
for 250us before entering HIBERNATE mode.
1648
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers

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