Infineon TRAVEO T2G - Page 328

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
25 NOCYCCNT RW R 0 Shows whether the implementation supports a cycle
counter:
0 Cycle counter supported.
1 Cycle counter not supported.
For more information see CYCCNT cycle counter and
related timers on Arm TRM page C1-792. This bit is
read-only.
26 NOEXTTRIG RW R 0 Shows whether the implementation includes external
match signals, CMPMATCH[N]:
0 CMPMATCH[N] supported.
1 CMPMATCH[N] not supported.
This bit is read-only.
27 NOTRCPKT RW R 0 Shows whether the implementation supports trace
sampling and exception tracing:
0 Trace sampling and exception tracing supported.
1 Trace sampling and exception tracing not supported.
If this bit is RAZ, the NOCYCCNT bit must also RAZ.
This bit is read-only.
28:31 NUMCOMP RW R 4 Number of comparators implemented.
A value of zero indicates no comparator support.
These bits are read-only.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers