Infineon TRAVEO T2G - Page 327

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
10:11 SYNCTAP RW R 0 Selects the position of the synchronization packet
counter tap on the CYCCNT counter. This determines
the Synchronization packet rate:
00 Disabled. No Synchronization packets.
01 Synchronization counter tap at CYCCNT[24].
10 Synchronization counter tap at CYCCNT[26].
11 Synchronization counter tap at CYCCNT[28].
For more information see The synchronization packet
timer on Arm TRM page C1-794.
This field is UNK/SBZP if the NOCYCCNT bit is RAO.
12 PCSAMPLENA RW R 0 Enables use of POSTCNT counter as a timer for
Periodic PC sample packet generation:
0 No Periodic PC sample packets generated.
1 Periodic PC sample packets generated.
See The POSTCNT timer on Arm TRM page C1-792
for more information.
This bit is UNK/SBZP if the NOTRCPKT bit is RAO or
the NOCYCCNT bit is RAO.
16 EXCTRCENA RW R 0 Enables generation of exception trace:
0 Disabled.
1 Enabled.
This bit is UNK/SBZP if the NOTRCPKT bit is RAO.
17 CPIEVTENA RW R 0 Enables generation of the CPI counter overflow event:
0 Disabled.
1 Enabled.
This bit is UNK/SBZP if the NOPRFCNT bit is RAO.
18 EXCEVTENA RW R 0 Enables generation of the Exception overhead counter
overflow event:
0 Disabled.
1 Enabled.
This bit is UNK/SBZP if the NOPRFCNT bit is RAO.
19 SLEEPEVTENA RW R 0 Enables generation of the Sleep counter overflow
event.
0 Disabled.
1 Enabled.
This bit is UNK/SBZP if the NOPRFCNT bit is RAO.
20 LSUEVTENA RW R 0 Enables generation of the LSU counter overflow event.
0 Disabled.
1 Enabled.
This bit is UNK/SBZP if the NOPRFCNT bit is RAO.
21 FOLDEVTENA RW R 0 Enables generation of the Folded-instruction counter
overflow event:
0 Disabled.
1 Enabled.
This bit is UNK/SBZP if the NOPRFCNT bit is RAO.
22 CYCEVTENA RW R 0 Enables POSTCNT underflow Event counter packets
generation:
0 No POSTCNT underflow packets generated.
1 POSTCNT underflow packets generated, if
PCSAMPLENA set to 0.
See The POSTCNT timer on Arm TRM page C1-792
for more information.
This bit is UNK/SBZP if the NOTRCPKT bit is RAO or
the NOCYCCNT bit is RAO.
24 NOPRFCNT RW R 0 Shows whether the implementation supports the
profiling counters:
0 Supported.
1 Not supported.
For more information see Profiling counter support on
Arm TRM page C1-794.
This bit is read-only.
327
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers