Infineon TRAVEO T2G - Page 706

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
26 OFC_MASK RW R 0 CPU FPU exception mask for the CPU's FPCSR.OFC
'overflow' exception condition:
'0': The CPU's exception condition does NOT activate
the CPU's floating point interrupt.
'1': the CPU's exception condition activates the CPU's
floating point interrupt.
27 UFC_MASK RW R 0 CPU FPU exception mask for the CPU's FPCSR.UFC
'underflow' exception condition:
'0': The CPU's exception condition does NOT activate
the CPU's floating point interrupt.
'1': the CPU's exception condition activates the CPU's
floating point interrupt.
28 IXC_MASK RW R 0 CPU FPU exception mask for the CPU's FPCSR.IXC
'inexact' exception condition:
'0': The CPU's exception condition does NOT activate
the CPU's floating point interrupt.
'1': the CPU's exception condition activates the CPU's
floating point interrupt.
Note: the 'inexact' condition is set as a result of
rounding. Rounding may occur frequently and is
typically not an error condition. To prevent frequent
CPU FPU interrupts as a result of rounding, this field is
typically set to '0'.
31 IDC_MASK RW R 0 CPU FPU exception mask for the CPU's FPCSR.IDC
'input denormalized' exception condition:
'0': The CPU's exception condition does NOT activate
the CPU's floating point interrupt.
'1': the CPU's exception condition activates the CPU's
floating point interrupt.
Note: if the CPU FPCSR.FZ field is set to '1',
denormalized inputs are 'flushed to zero'. Dependent
on the FPU algorithm, this may or may not occur
frequently. To prevent frequent CPU FPU interrupts as
a result of denormalized inputs, this field may be set to
'0'.
706
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers