Infineon TRAVEO T2G - Page 1707

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
30 SLEEPDEEP_PAUSE RW R 0 Pauses/runs this counter when the corresponding
processor is in SLEEPDEEP. Note it may take up to
two clk_lf cycles for the counter to pause and up to two
clk_lf cycles for it to unpause, due to internal
synchronization.
0: Counter runs normally regardless of processor
mode.
1: Counter pauses when corresponding processor is in
SLEEPDEEP.
31 DEBUG_RUN RW R 0 Pauses/runs this counter while a debugger is
connected. Other behaviors are unchanged during
debugging, including service, configuration updates
and enable/disable. Note it may take up to two clk_lf
cycles for the counter to pause and another two cycles
to unpause, due to internal synchronization.
0: When debugger connected, counter pauses
incrementing as configured in DEBUG_TRIGGER_EN.
1: When debugger connected, counter increments
normally, but reset generation is blocked.
1707
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers