Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
17 MAIN_ECC_INJ_EN RW R 0 Enable error injection for FLASH main interface.
When'1', the parity (ECC_CTL.PARITY[7:0]) is used
for a load from the ECC_CTL.WORD_ADDR[23:0]
word address.
18 MAIN_ERR_SILENT RW R 0 Specifies bus transfer behavior for a non-recoverable
error on the FLASH macro main interface (either a
non-correctable ECC error, a FLASH macro main
interface internal error, a FLASH macro main interface
memory hole access):
0: Bus transfer has a bus error.
1: Bus transfer does NOT have a bus error; i.e. the
error is 'silent'
In either case, the erroneous FLASH macro data is
returned by the bus master interface. The erroneous
data is NOT placed in a bus master interface's cache
and/or buffer.
This field is ONLY used by CPU (and debug i.e.
SYS_AP/CM0_AP/CM4_AP) bus transfers. Non-CPU
bus transfers always have a bus transfer with a bus
error, in case of a non-recoverable error.
Note: All CPU bus masters have dedicated status
registers (CM0_STATUS and CM4_STATUS) to
register the occurrence of FLASH macro main
interface internal errors (non-correctable ECC errors
and memory hole errors are NOT registered).
Note: fault reporting can be used to identify the error
that occurred:
- FLASH macro main interface internal error.
- FLASH macro main interface non-recoverable ECC
error.
- FLASH macro main interface recoverable ECC error.
- FLASH macro main interface memory hole error.
20 WORK_ECC_EN RW R 1 Enable ECC checking for FLASH work interface:
0: Disabled. ECC checking/reporting on FLASH work
interface is disabled. No correctable or non-correctable
faults are reported.
1: Enabled.
21 WORK_ECC_INJ_EN RW R 0 Enable error injection for FLASH work interface.
When'1', the parity (ECC_CTL.PARITY[6:0]) is used
for a load from the ECC_CTL.WORD_ADDR[23:0]
word address.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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