Infineon TRAVEO T2G - Page 1333

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
5 PX R R 0 Privileged execute enable:
'0': Disabled (privileged, execute accesses are NOT
allowed).
'1': Enabled (privileged, execute accesses are
allowed).
Note that this register is constant '0'; i.e. privileged
execute accesses are NEVER allowed.
6 NS RW R Undefined Non-secure:
'0': Secure (secure accesses allowed, non-secure
access NOT allowed).
'1': Non-secure (both secure and non-secure accesses
allowed).
8 PC_MASK_0 R R 1 This field specifies protection context identifier based
access control for protection context '0'.
9:23 PC_MASK_15_TO_1 RW R Undefined This field specifies protection context identifier based
access control.
Bit i: protection context i+1 enable. If '0', protection
context i+1 access is disabled; i.e. not allowed. If '1',
protection context i+1 access is enabled; i.e. allowed.
24:28 REGION_SIZE R R 7 This field specifies the region size:
'7': 256 B region (8 32 B subregions)
Note: this field is read-only.
30 PC_MATCH RW R Undefined This field specifies if the PC field participates in the
'matching' process or the 'access evaluation' process:
'0': PC field participates in 'access evaluation'.
'1': PC field participates in 'matching'.
'Matching' process. For each protection structure, the
process identifies if a transfer address is contained
within the address range. This identifies the 'matching'
regions.
'Access evaluation' process. For each protection
structure, the process evaluates the bus transfer
access attributes against the access control attributes.
Note that it is possible to define different access
control for multiple protection contexts by using
multiple protection structures with the same address
region and PC_MATCH set to '1'.
31 ENABLED RW R 0 Region enable:
'0': Disabled. A disabled region will never result in a
match on the bus transfer address.
'1': Enabled.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers