Infineon TRAVEO T2G - Page 1062

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
0 TX_HEADER_DONE RW1C RW1S 0 HW sets this field to '1', when a frame header (break
field, synchronization field and PID field) is transmitted
(the CMD.TX_HEADER is completed). Specifically:
- When followed by CMD.TX_RESPONSE or
CMD.RX_RESPONSE, this field is set to '1' after
completion of the frame header transfer.
- When not followed by a response command, this field
is set to '1' after completion of the frame header
transfer. If CTL.AUTO_EN is '1', this includes the 4-bit
period external transceiver disable post-amble.
Note: used in UART mode.
1 TX_RESPONSE_DONE RW1C RW1S 0 HW sets this field to '1', when a frame response (data
fields and checksum field) is transmitted (the
CMD.TX_RESPONSE is completed). If
CTL.AUTO_EN is '1', this includes the 4-bit period
external transceiver disable post-amble.
2 TX_WAKEUP_DONE RW1C RW1S 0 HW sets this field to '1', when a wakeup signal is
transmitted (per CTL.BREAK_WAKEUP_LENGTH).
This cause is activated on a transition from
dominant/'0' state to recessive/'1' state; i.e. at the end
of the wakeup signal.
8 RX_HEADER_DONE RW1C RW1S 0 HW sets this field to '1', when a frame header (break
field, synchronization field and PID field) is received
(the CMD.RX_HEADER is completed). Specifically:
- When followed by CMD.TX_RESPONSE or
CMD.RX_RESPONSE, this field is set to '1' after
completion of the frame header transfer.
- When not followed by a response command, this field
is set to '1' after completion of the frame header
transfer. If CTL.AUTO_EN is '1', this includes the 4-bit
period external transceiver disable post-amble.
Note: used in UART mode.
9 RX_RESPONSE_DONE RW1C RW1S 0 HW sets this field to '1', when a frame response (data
fields and checksum field) is received (the
CMD.RX_RESPONSE is completed). If
CTL.AUTO_EN is '1', this includes the 4-bit period
external transceiver disable post-amble.
Note: activation implies that
RX_RESPONSE_FRAME_ERROR and
RX_RESPONSE_CHECKSUM_ERROR are not
activated during response reception
10 RX_BREAK_WAKEUP
_DONE
RW1C RW1S 0 HW sets this field to '1', when a break or wakeup
signal is received (per
CTL.BREAK_WAKEUP_LENGTH). This cause is
activated on a transition from dominant/'0' state to
recessive/'1' state; i.e. at the end of the wakeup signal.
The break or wakeup detection is always enabled,
regardless of CMD register setting.
11 RX_HEADER_SYNC
_DONE
RW1C RW1S 0 HW sets this field to '1', when a synchronization field is
received (including trailing STOP bits).
1062
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers