Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
8:15 RTO R RW 0 Reference Trigger Offset
The Reference Trigger Offset value is a signed integer
with a range from -127 (0x81) to 127 (0x7F).
There is no notification when the lower limit of -127 is
reached. In case the M_TTCAN becomes
Time Master (MS[1:0] = '11'), the reset of RTO is
delayed due to synchronization between Host and
CAN clock domain. For time slaves the value
configured by TTOCF.IRTO is read.
0x00-FF Actual Reference Trigger offset value
22 WGTD R RW 0 Wait for Global Time Discontinuity
0= No global time preset pending
1= Node waits for the global time preset to take effect.
The bit is reset when the node has transmitted
a reference message with Disc_Bit = '1' or after it
received a reference message.
23 GFI R RW 0 Gap Finished Indicator
Set when the CPU writes TTOCN.FGP, or by a time
mark interrupt if TMG = '1', or via input pin
m_ttcan_evt if TTOCN.GCS = '1'. Not set by
Ref_Trigger_Gap or when Gap is finished by another
node sending a reference message.
0= Reset at the end of each reference message
1= Gap finished by M_TTCAN
24:26 TMP R RW 0 Time Master Priority
0x0-7 Priority of actual Time Master
27 GSI R RW 0 Gap Started Indicator
0= No Gap in schedule, reset by each reference
message and for all time slaves
1= Gap time after Basic Cycle has started
28 WFE R RW 0 Wait for Event
0= No Gap announced, reset by a reference message
with Next_is_Gap = '0'
1= Reference message with Next_is_Gap = '1'
received
29 AWE R RW 0 Application Watchdog Event
The application watchdog is served by reading
TTOST. When the watchdog is not served in time,
bit AWE is set, all TTCAN communication is stopped,
and the M_TTCAN is set into Bus Monitoring
Mode.
0= Application Watchdog served in time
1= Failed to serve Application Watchdog in time
30 WECS R RW 0 Wait for External Clock Synchronization
0= No external clock synchronization pending
1= Node waits for external clock synchronization to
take effect. The bit is reset at the start of the
next basic cycle.
31 SPL R RW 0 Schedule Phase Lock
The bit is valid only when external synchronization is
enabled (TTOCN.ESCN = '1'). In this case it
signals that the difference between cycle time
configured by TTGTP.CTP and the cycle time at the
rising edge at pin m_ttcan_evt is less or equal 9 NTU
(see Section 4.11).
0= Phase outside range
1= Phase inside range
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
To Next Page
Loading...
