Infineon TRAVEO T2G - Page 1284

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
4 PC0_NS R R 1 Protection context 0, non-secure:
'0': Secure (secure accesses allowed, non-secure
access NOT allowed).
'1': Non-secure (both secure and non-secure accesses
allowed).
8 PC1_UR RW R 1 Protection context 1, user read enable.
9 PC1_UW RW R 1 Protection context 1, user write enable.
10 PC1_PR RW R 1 Protection context 1, privileged read enable.
11 PC1_PW RW R 1 Protection context 1, privileged write enable.
12 PC1_NS RW R 1 Protection context 1, non-secure.
16 PC2_UR RW R 1 Protection context 2, user read enable.
17 PC2_UW RW R 1 Protection context 2, user write enable.
18 PC2_PR RW R 1 Protection context 2, privileged read enable.
19 PC2_PW RW R 1 Protection context 2, privileged write enable.
20 PC2_NS RW R 1 Protection context 2, non-secure.
24 PC3_UR RW R 1 Protection context 3, user read enable.
25 PC3_UW RW R 1 Protection context 3, user write enable.
26 PC3_PR RW R 1 Protection context 3, privileged read enable.
27 PC3_PW RW R 1 Protection context 3, privileged write enable.
28 PC3_NS RW R 1 Protection context 3, non-secure.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers