Infineon TRAVEO T2G - Page 1441

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
8 I2C_BUS_ERROR RW1C RW1S 0 I2C slave bus error (unexpected detection of START
or STOP condition). This should not occur, it
represents erroneous I2C bus behavior. In case of a
bus error, the I2C slave state machine abort the
ongoing transfer. The Firmware may decide to clear
the TX and RX FIFOs in case of this error.
9 SPI_EZ_WRITE_STOP RW1C RW1S 0 SPI slave deselected after a write EZ SPI transfer
occurred.
10 SPI_EZ_STOP RW1C RW1S 0 SPI slave deselected after any EZ SPI transfer
occurred.
11 SPI_BUS_ERROR RW1C RW1S 0 SPI slave deselected at an unexpected time in the SPI
transfer. The Firmware may decide to clear the TX and
RX FIFOs in case of this error.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers