Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
PATH10 10 Select PATH10 (can be configured for PLL9, if
available in the product)
PATH11 11 Select PATH11 (can be configured for PLL10, if
available in the product)
PATH12 12 Select PATH12 (can be configured for PLL11, if
available in the product)
PATH13 13 Select PATH13 (can be configured for PLL12, if
available in the product)
PATH14 14 Select PATH14 (can be configured for PLL13, if
available in the product)
PATH15 15 Select PATH15 (can be configured for PLL14, if
available in the product)
4:5 ROOT_DIV RW R 0 Selects predivider value for this clock root and DSI
input. This divider is after DIRECT_MUX. For products
with DSI, the output of this mux is routed to DSI for use
as a signal. For products with clock supervision, the
output of this mux is the monitored clock for
CSV_HF<k>.
NO_DIV 0 Transparent mode, feed through selected clock source
w/o dividing.
DIV_BY_2 1 Divide selected clock source by 2
DIV_BY_4 2 Divide selected clock source by 4
DIV_BY_8 3 Divide selected clock source by 8
8 DIRECT_MUX RW A (1 << int
ernals.reg
_index & M
ASK
_DIRECT
MUX_DEF)
>> internal
s.reg_index
Direct selection mux that allows IMO to bypass most of
the clock mux structure. For products with multiple
regulators, this mux can be used to reduce current
without requiring significant reconfiguration of the
clocking network. The default value of
HFCLK<0>==ROOT_MUX, and the default value for
other clock trees is product-specific.
IMO 0 Select IMO
ROOT_MUX 1 Select ROOT_MUX selection
31 ENABLE RW A 0 Enable for this clock root. All clock roots default to
disabled (ENABLE==0) except HFCLK0, which cannot
be disabled.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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