Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
27 BIT_ERROR_IGNORE RW R 0 Specifies behavior on a detected bit error during
header or response transmission:
'0': Message transfer is aborted.
'1': Message transfer is NOT aborted.
Note: This field does NOT effect the reporting of the bit
error through INTR/STATUS.TX_BIT_ERROR; i.e. bit
errors are always reported.
Note: This field must not be set to '1' when it is NRZ
mode. This is due to delay in transceiver will cause the
transmitter behavior undefined when error occurs.
ABORT_TX_MSG 0 Message transfer is aborted
CONT_TX_MSG 1 Message transfer is NOT aborted
30 MASTER RW R 0 CXPI master mode.
'0': Indicates CXPI as slave node.
'1': Indicates CXPI as master node.
This bit is only valid if ENABLED=1. SW needs to set
only 1 node as master within the same CXPI cluster.
SW needs to set this bit either at the same time as
ENABLED or before ENABLED is set. If SW needs to
change the controller to different mode, it needs to
make sure that HW is quiescent before doing so.
SLAVE_MODE 0 Slave mode
MASTER_MODE 1 Master mode
31 ENABLED RW R 0 Channel enable:
'0': Disabled. If a channel is disabled, CMD, STATUS,
INTR MMIO registers will have their fields reset to their
default value.
'1': Enabled.
DISABLED 0 Disabled
ENABLED 1 Enabled
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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