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Infineon TRAVEO T2G
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Technical Reference Manual 002-29852 Rev. *B
Name None [15:10] RX
_RESPON
SE [9:9]
RX
_HEADER
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 TX_HEADER RW RW 0 SW sets this field to '1' to transmit a header. HW sets
this field to '0' on successful completion of ANY of the
following legal command sequences (also set to '0'
when an error (such as bit error if bit_ignore=0,
arbitration loss, tx data length error. For timeout please
refer to SAS) is detected):
- TX_HEADER
- TX_HEADER, TX_RESPONSE.
- TX_HEADER, RX_RESPONSE.
The above is for transmission of PID without prior
transmission of PTYPE.
The header is transmitted when the PID field STOP
bits are transmitted (INTR.TX_HEADER_DONE).
HW sets this field to '1', when the 'tr_cmd_tx_header'
input trigger is activated. This allows for time triggered
CXPI message transfer. HW driven time triggered
transfer eliminates the jitter that is typically associated
with SW driven transfer.
SW clears this field to '0', when it wants to cancel a
pending request. Note that if SW clears this field to '0'
while HW is already in the middle of the request, then
the cancel will be ignored. The cancel request can
happen when HW is pending a retry when it is still
servicing the current transaction. Or the cancel request
can occur when HW is checking IFS/bus idle-ness.
Note that if PTYPE (TX_HEADER) is transmitted
follow by receive response (RX_RESPONSE) or no
response, HW clears TX_HEADER right after
transmitting PTYPE.
1 TX_RESPONSE RW RW1C 0 SW sets this field to '1' to transmit a response. HW
sets this field to '0' on successful completion of ANY of
the legal command sequences (also set to '0' when an
error is detected).
- TX_HEADER, TX_RESPONSE.
- RX_HEADER, TX_RESPONSE.
SW can also clear this field to '0' if SW wants to cancel
the TX_RESPONSE.
The response is transmitted when the CRC are
transmitted (INTR.TX_RESPONSE_DONE).
776
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers

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