Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
27 DST_TRANSFER_SIZE R W Undefined Specifies the bus transfer size to the destination
location:
'0': As specified by DATA_SIZE.
'1': Word (32 bits).
Distinguishing bus transfer size from data element size
allows for destination components with data elements
that are smaller than their 32-bit bus interface width.
E.g., a DAC destination has a 32-bit bus transfer size,
but only requires a 16-bit data element.
Note: this field is not used for a 'memory copy'
descriptor type. Note: this field must be set to '1' for a
'scatter' descriptor type.
28:30 DESCR_TYPE R W Undefined Specifies the descriptor type (not to be confused with
the trigger type):
'0': Single transfer.
The DESCR_X_SIZE, DESCR_X_INCR,
DESCR_Y_SIZE and DESCR_Y_INCR registers are
NOT present. The DESCR_NEXT_PTR is at offset
0x0c.
'1': 1D transfer.
The DESCR_X_SIZE and DESCR_X_INCR registers
are present, the DESCR_Y_SIZE and
DESCR_Y_INCR are NOT present. A 1D transfer
consists out of DESCR_X_SIZE.X_COUNT+1 single
transfers. The DESCR_NEXT_PTR is at offset 0x14.
'2': 2D transfer.
The DESCR_X_SIZE, DESCR_X_INCR,
DESCR_Y_SIZE and DESCR_Y_INCR registers are
present. A 2D transfer consists of
(DESCR_X_SIZE.X_COUNT+1)*(DESCR_Y_SIZE.Y_COUNT+1)
single transfers. The DESCR_NEXT_PTR is at offset
0x1c.
'3': Memory copy.
The DESCR_X_SIZE register is present, the
DESCR_X_INCR, DESCR_Y_SIZE and
DESCR_Y_INCR are NOT present. A memory copy
transfer copies DESCR_X_SIZE.X_COUNT+1 Bytes
and may use Byte, halfword and word transfers. The
DESCR_NEXT_PTR is at offset 0x10.
'4': Scatter transfer. The DESCR_X_SIZE register is
present, the DESCR_DST, DESCR_X_INCR,
DESCR_Y_SIZE and DESCR_Y_INCR are NOT
present.
'5'-'7': Undefined.
After the execution of the current descriptor, the
DESCR_NEXT_PTR address is copied to the
channel's CH_CURR_PTR address and
CH_STATUS.X_IDX and CH_STATUS.Y_IDX are set
to '0'.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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