Infineon TRAVEO T2G - Page 1047

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
27 BIT_ERROR_IGNORE RW R 0 Specifies behavior on a detected bit error during
header or response transmission:
'0': Message transfer is aborted.
'1': Message transfer is NOT aborted.
Note: this field does NOT effect the reporting of the bit
error through
INTR/STATUS.TX_HEADER/RESPONSE_BIT_ERROR;
i.e. bit errors are always reported.
28 PARITY RW R 0 Parity mode:
'0': Even parity: even number of '1' bits (including
parity).
'1': Odd parity.
Note: Used in UART mode only.
29 PARITY_EN RW R 0 Parity generation enable:
'0': Disabled. No parity bit is transferred.
'1': Enabled. The parity bit is transferred after the last
(most significant) data field bit.
Note: Used in UART mode only.
30 FILTER_EN RW R 1 RX filter (for 'lin_rx_in'):
'0': No filter.
'1': Median 3 (default value) operates on the last three
'lin_rx_in' values. The sequences '000', '001', '010' and
'100' result in a filtered value '0'. The sequences '111',
'110', '101' and '011' result in a filtered value '1'.
31 ENABLED RW R 0 Channel enable:
'0': Disabled. If a channel is disabled, all non-retained
MMIO registers (e.g. the TX_RX_STATUS, and INTR
registers) have their fields reset to their default value.
'1': Enabled.
1047
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers