Infineon TRAVEO T2G - Page 68

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
21 BEU RW1C RW 0 Bit Error Uncorrected
Message RAM bit error detected, uncorrected. The
flag is set in the folloiwng cases.
- M_TTCAN detects uncorrectable ECC error from
Message RAM when ECC is enabled and ECC error
injection is disabled.
- M_TTCAN reads from an out of range Message RAM
address.
Message RAM bit error sets CCCR.INIT to '1'. This is
done to avoid transmission of corrupted data.
0= No bit error detected when reading from Message
RAM
1= Bit error detected, uncorrected
22 ELO RW1C RW 0 Error Logging Overflow
0= CAN Error Logging Counter did not overflow
1= Overflow of CAN Error Logging Counter occurred
23 EP_ RW1C RW 0 Error Passive
0= Error_Passive status unchanged
1= Error_Passive status changed
24 EW_ RW1C RW 0 Warning Status
0= Error_Warning status unchanged
1= Error_Warning status changed
25 BO_ RW1C RW 0 Bus_Off Status
0= Bus_Off status unchanged
1= Bus_Off status changed
26 WDI RW1C RW 0 Watchdog Interrupt
0= No Message RAM Watchdog event occurred
1= Message RAM Watchdog event due to missing
READY
27 PEA RW1C RW 0 Protocol Error in Arbitration Phase (Nominal Bit Time
is used)
0= No protocol error in arbitration phase
1= Protocol error in arbitration phase detected
(PSR.LEC != 0,7)
28 PED RW1C RW 0 Protocol Error in Data Phase (Data Bit Time is used)
0= No protocol error in data phase
1= Protocol error in data phase detected (PSR.DLEC
!= 0,7)
29 ARA RW1C RW 0 Access to Reserved Address
0= No access to reserved address occurred
1= Access to reserved address occurred
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers