Infineon TRAVEO T2G - Page 863

Technical Reference Manual
Bits Name SW HW Default or
Enum
Description
(Continuation)
-
If the descriptor type is 'single', the trigger results in
the execution of a single transfer.
-
If the descriptor type is '1D' or '2D', the trigger results
in the execution of a 1D transfer.
'2': A
trigger results in the execution of the current
descriptor.
'3': A
trigger results in the execution of the current
descriptor and continues (without requiring another
input trigger) with the execution of the next descriptor
using the next descriptor's information.
[
29:28]
DATA_SIZE
Specifies the
data element size:
'0': Byte (8 bits).
'1': Halfword (16 bits).
'2': Word (32 bits).
DATA_SIZE,
SRC_TRANSFER_SIZE and
DST_TRANSFER_SIZE
together determine how data
elements
are transferred. The following are the 9 legal
settings:
- DATA is
8 bit, SRC is 8 bit, DST is 8 bit.
- DATA is
8 bit, SRC is 32 bit (higher 24 bits are
dropped), DST is 8 bit.
- DATA is
8 bit, SRC is 8 bit, DST is 32 bit (higher 24bits are
made '0').
- DATA is
8 bit, SRC is 32 bit (higher 24 bits are
dropped), DST is 32 bit (higher 24 bits are made '0').-
DATA is 16 bit, SRC is 16 bit, DST is 16 bit.
-
DATA is
16 bit, SRC is 32 bit (higher 16 bits are
dropped), DST is 16 bit.
- DATA is
16 bit, SRC is 16 bit, DST is 32 bit (higher
16 bits are made '0').
- DATA is
16 bit, SRC is 32 bit (higher 16 bits are
dropped), DST is 32 bit (higher 16 bits are made '0').
- DATA is
32 bit, SRC is 32 bit, DST
002-
is 32 bit.
[31:30] DESCR_TYPE
Specifies the descriptor type (not to be confused withthe trig
ger type):
'0': Single transfer. The DESCR_X_CTL and
DESCR_Y_CTL registers are not present and
DESCR_NEXT_PTR is at offset 0x0c.
[27] DST_TRANSFER_SIZE
Specifies
the bus transfer size to the destination
location:
'0': As specified by DATA_SIZE.
'1': Word (32 bits).
Distinguishing
bus transfer size from data element size
all
ows for destination components with data elements
that
ar
e smaller than their 32-bit bus interface width.
E.g., a DAC destination has a 32-bit bus transfer size,but
only requires
a
16-bit data element.
[26] SRC_TRANSFER_SIZE
Specifies the bus transfer size to the source location:'0': As s
pecified by
DATA_SIZE.
'1': Word (32 bits).
Distinguishing bus transfer size from data element size
allows for source components with data elements that
are
smaller than their 32-bit bus interface width. E.g.,an ADC
s
ource has a 32-bit bus transfer size, but only
provides a 16-bit data element.
Note:
a disabled channel will ignore its input trigger.
[24] CH_DISABLE
Specifies whether
the channel is disabled or not after
completion of the current descriptor (independent of the
value
of the DESCR_NEXT_PTR value):
'0':
Channel is not disabled.
'1': Channel is disabled.
002-29852 Rev. *B
863
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers