Infineon TRAVEO T2G - Page 864

Technical Reference Manual 002-29852 Rev. *B
Bits Name SW HW Default or
Enum
Description
(Continuation)
'1': 1D transfer. The DESCR_X_CTL register is
present, the DESCR_Y_CTL is not present and
DESCR_NEXT_PTR is at offset 0x10. A 1D transfer
consists out of DESCR_X_CTL.X_COUNT single
transfers.
'2': 2D transfer. The DESCR_X_CTL and
DESCR_Y_CTL registers are present and
DESCR_NEXT_PTR is at offset 0x14. A 2D transfer
consists of
DESCR_X_CTL.X_COUNT*DESCR_Y_CTL.Y_COUNT
single transfers.
'3': CRC transfer. The DESCR_X_CTL register is
present, theDESCR_Y_CTL is not present and
DESCR_NEXT_PTR is at offset 0x10. A CRC transfer
consists out of DESCR_X_CTL.X_COUNT single
transfers.
After the execution of the current descriptor, the
DESCR_NEXT_PTR address is copied to the
channel's CH_CURR_PTR address and
CH_STATUS.X_IDX and CH_STATUS.Y_IDX are set
to '0'.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers