RM0046 Clock Description
Doc ID 16912 Rev 5 105/936
4.8.6 Functional description
Normal mode
In Normal mode, the PLL inputs are driven by the Control Register (CR). This means that
when the PLL is locked, the PLL output clock (PHI) is derived from the reference clock
(XOSC) through this relationship:
Equation 1
where the value of idf (Input Division Factor), ldf (Loop Division Factor), and odf (Output
Division Factor) are set in the CR as shown in Ta ble 13. idf and odf are specified in the IDF
and ODF bitfields, respectively; ldf is specified in the NDIV bitfield.
Progressive clock switching
Progressive clock switching allows to switch system clock to PLL output clock stepping
through different division factors. This means that the current consumption gradually
increases and, in turn, voltage regulator response is improved.
This feature can be enabled by programming bit en_pll_sw in the CR. Then, when the PLL is
selected as the system clock, the output clock progressively increases its frequency as
shown in Tabl e 15 .
MOD_PERIOD
Modulation period
The MOD_PERIOD field is the binary equivalent of the value modperiod derived from following
formula:
where:
fref: represents the frequency of the feedback divider
fmod: represents the modulation frequency
FM_EN
Frequency modulation enable
The FM_EN bit enables the frequency modulation.
0: Frequency Modulation disabled
1: Frequency Modulation enabled
INC_STEP
Increment step
The INC_STEP field is the binary equivalent of the value incstep derived from following formula:
where:
md: represents the peak modulation depth in percentage
(Center spread — pk-pk = ±md, Downspread — pk-pk = –2 × md)
MDF: represents the nominal value of loop divider (NDIV in PLL Control Register).
Table 14. MR field descriptions (continued)
Field Description
modperiod
f
ref
4f
mod
---------------------=
incstep round
2
15
1–md MDF
100 5 MODPERIOD
-----------------------------------------------------------------
=
phi
xosc ldf
idf odf
------------------------=
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