RM0046 Clock Description
Doc ID 16912 Rev 5 95/936
4.2.2 Clock selectors
System clock selector 0 for SYS_CLK
The system clock selector 0 selects the clock source for the system clock (SYS_CLK) from
clock signals:
● Internal RC oscillator clock (IRC)
● Progressive output clock of FMPLL_0
● Directly from the oscillator clock (XOSC)
Its behavior is configured via software through ME_x_MC register of the ME module.
When the standard boot from internal flash is selected via the boot configuration pins, the
clock source for the system clock (SYS_CLK) after reset (DRUN mode) is the internal RC
oscillator (IRC).
4.2.3 Auxiliary Clock Selector 0
There is no Auxiliary Clock present on SPC560P40/34 device, but to maintain the software
compatibility, corresponding register in MC_CGM (CGM_AC0_SC) has been implemented
through which user can select any clock source from the given auxiliary clock sources. As
there is no auxiliary clock, all the auxiliary clock sources have been tied to ‘0’.
4.2.4 Auxiliary Clock Selector 1
There is no Auxiliary Clock present on SPC560P40/34 device, but to maintain the software
compatibility, corresponding register in MC_CGM (CGM_AC1_SC) has been implemented
through which user can select any clock source from the given auxiliary clock sources. As
there is no auxiliary clock, all the auxiliary clock sources have been tied to ‘0’.
4.2.5 Auxiliary Clock Selector 2
There is no Auxiliary Clock present on SPC560P40/34 device, but to maintain the software
compatibility, corresponding register in MC_CGM (CGM_AC2_SC) has been implemented
through which user can select any clock source from the given auxiliary clock sources. As
there is no auxiliary clock, all the auxiliary clock sources have been tied to ‘0’.
4.2.6 Auxiliary clock dividers
As there is no auxiliary clock present on SPC560P40/34, there is no point in having the
auxiliary clock dividers. To maintain the software compatibility, one divider corresponding to
every auxiliary clock has been implemented. Corresponding registers have been
implemented in MC_CGM which can be accessed by user but have no impact in device.
These registers are CGM_AC0_DC0, CGM_AC1_DC0, and CGM_AC2_DC0
4.2.7 External clock divider
The output clock divider provides a nominal 50% duty cycle clock and allows the selected
output clock source to be divided with these divide options:
● ÷1, ÷2, ÷4, ÷8
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